A 96-channel TDC (Time to Digital Converter) VME board was
designed for the CDF detector in Tevatron Collider Run II at Fermilab. The
features include: a custom ASIC (Application Specific Integrated Circuit)
component that provides time measurements of signals from the various
detector elements; a DSP (Digital Signal Processor) that formats the
digitized data sent to the data acquisition system; a built-in diagnostic
system; a VME interface to read out the data and control the board
configuration. This TDC board implements the CDF data acquisition and
trigger protocols. The TDCs were designed initially to achieve 300 Hz
readout rate. More than 400 of these TDCs provide 1 ns resolution timing
for signal pulses from wire chambers, scintillator panels, and calorimeter
towers. In addition, custom daughter boards connected to the TDCs provide
data to the level-1 trigger system. We describe the functionality of the
TDC boards and performances during Run II operation.
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Updated: Tuesday, 2005 January 04 11:25:30 CST automatically from input from Carol Picciolo