The Fanout system is part of the Silicon Vertex Tracker, a new
trigger processor designed to reconstruct charged particle trajectories at
Level 2 of the CDF trigger, with a latency of 10 mu s and an event rate up
to 100 kHz. The core of SVT is organized as 12 identical slices, which
process in parallel the data from the 12 independent azimuthal wedges of the
Silicon Vertex Detector (SVXII). Each SVT slice links the digitized pulse
heights found within one SVXII wedge to the tracks reconstructed by the
Level 1 fast track finder (XFT) in the corresponding 300 angular region of
the Central Outer Tracker. Since the XFT tracks are transmitted to SVT as a
single data stream, their distribution to the proper SVT slices requires
dedicated fanout logic. The Fanout system has been implemented as a
multiboard project running on a common 20 MHz clock. Track fanout is
performed in two steps by one "Fanout A" and two "Fanout B" boards. The
architecture, design, and implementation of this system are described.
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Updated: Monday, 2001 October 01 14:41:23 CDT automatically from input from Carol Picciolo